Cerebras Systems has unveiled a new AI accelerator that delivers twice the performance of its predecessor simply by running the existing silicon harder, according to a report published by The Register on Tuesday. The company's WSE-3T chip—where the "T" stands for "Turbo"—achieves 250 petaFLOPS of sparse compute and 43.2 petabytes per second of memory bandwidth without adding more transistors or changing the manufacturing process. Instead, the chipmaker appears to have roughly doubled the clock speed from 1.4 GHz to an estimated 2.8 GHz through improved power delivery.
The new chip uses the same TSMC 5nm process, 46,225 square millimeter wafer area, 4 trillion transistors, 900,000 cores, and 44 GB of on-chip SRAM as the two-year-old WSE-3, according to specifications published in the report. What's changed is power consumption: the wafer-level thermal design power jumps from 15 kilowatts to an estimated 33 kW, while system-level power climbs from 23 kW to around 46 kW. The doubled power budget enables higher operating frequencies and faster token generation, the report notes. The chip's dense FP16 performance sits at approximately 25 petaFLOPS when accounting for sparsity, compared to the 4 to 5 petaFLOPS offered by the latest GPUs from AMD and Nvidia at the same precision.
The report finds that Cerebras is no longer attempting to run the entire inference workload on its own accelerators. Instead, the company has partnered with Amazon Web Services and AMD to offload compute-intensive prompt processing to their Trainium chips and Instinct GPUs, leaving Cerebras' accelerators to function primarily as decode chips. The new CS-4 rack system can house up to three chip "backpacks" and achieves speeds of up to 4,400 tokens per second per user running the gpt-oss-120b model on a single system, compared to around 350 tokens per second on the fastest GPU-based inference service today, according to benchmarking data cited in the report. Cerebras has also cut chip-to-chip latency from five microseconds down to two by eliminating switches and using a 2D torus mesh where chips communicate directly with one another.
The decision to boost performance rather than expand SRAM capacity—which hasn't increased meaningfully since the WSE-2 launched five years ago—likely reflects production timelines that predated the recent shift toward disaggregated inference architectures, the report suggests. In an environment where prefill is handled by GPUs, prioritizing memory capacity over raw compute would make more sense, since Cerebras' main advantage is the enormous amount of on-chip SRAM that lets it run trillion-parameter models with far fewer accelerators than competing approaches require. The topology supports models up to 50 trillion parameters, though no such model currently exists. The first CS-4 systems are expected to come online later this quarter, with total rack power consumption estimated between 120 kW and 140 kW—modest compared to the 240 to 250 kW systems coming from AMD and Nvidia later this year. For organizations evaluating inference infrastructure, the choice between monolithic high-memory chips and distributed GPU clusters now hinges on whether latency or flexibility matters more for their workload mix.