Commercially available RISC-V processors are vulnerable to all major variants of Spectre security flaws, contradicting widespread assumptions that the chip architecture's simplicity protects it from such attacks, according to a paper accepted at the 35th Usenix Security Symposium and reported by The Register. Researchers from academic institutions in Belgium and Germany demonstrated successful Spectre exploits on out-of-order RISC-V processors, leaking Linux kernel memory at 338 bytes per second. The findings reveal that RISC-V technology faces the same microarchitectural security risks that have plagued x86 and ARM chips since 2018, but lacks the defensive infrastructure built up over eight years.
The research team tested multiple RISC-V processors and found that out-of-order models—specifically the SiFive P550 and T-Head Xuantie C910/C920—are susceptible to all major Spectre variants. The attacks achieved up to 100 percent recall with more than 97 percent precision. In-order RISC-V processors, including the SiFive U74 and Xuantie C906 and C908 models, don't appear vulnerable. The researchers successfully deployed four different Spectre attack types: Spectre-PHT, which mistrains the Pattern History Table; Spectre-BTB, which poisons the Branch Target Buffer; Spectre-RSB, targeting the Return Stack Buffer; and Spectre-STL, exploiting mispredicted store-to-load forwarding. Previous academic research had shown vulnerabilities in RISC-V processors used for university research purposes, but this marks the first demonstration on commercial silicon.
"RISC-V inherits the software and threat model of mature architectures without their accumulated hardening," the authors conclude in the paper. The researchers point out that software defenses developed for x86 and ARM hardware don't necessarily transfer to RISC-V systems. They also criticize RISC-V hardware for lacking introspection interfaces needed to observe and understand microarchitectural features. The diversity of the RISC-V hardware ecosystem means no single defense strategy will likely work across all systems, according to the paper. The authors argue that addressing the problem requires "building the architectural primitives, hardware transparency, and ecosystemwide tooling that effective Spectre defense presupposes."
Spectre vulnerabilities stem from speculative execution, a performance optimization that predicts data flow before instructions finish running. When predictions prove wrong, they're rolled back without affecting applications, but traces remain that attackers can exploit to bypass memory protections and steal secrets. The research highlights a fundamental gap: RISC-V has adopted the performance features of established chip designs without inheriting the security hardening those platforms developed over years of response to Spectre attacks. The authors disclosed their findings responsibly in December 2025, and three patches have been merged into mainline Linux, with two more under review. SiFive has addressed P550-specific issues, while T-Head, owned by Alibaba, has committed to publishing speculation barriers for their processors, though no timeline was specified.
The researchers decided not to delay publication because Spectre has existed for eight years. The paper was written by Lukas Gerlach and Daniel Weber and Michael Schwarz from CISPA Helmholtz Center for Information Security, along with Marton Bognar and Jo Van Bulck from DistriNet at KU Leuven. The findings suggest that closing the security gap isn't simply a matter of porting individual fixes from x86 and ARM platforms. Organizations deploying RISC-V processors in production environments will need to weigh the architecture's promise of open-source flexibility against the reality that its security tooling remains years behind established alternatives, forcing a choice between innovation and battle-tested protection at a moment when both feel essential.