Security researcher Christopher Domas has released skitter-creek-bath-salts, an open-source hardware security project that breaks through traditional CPU security barriers by targeting memory controller translation registers. The tool manipulates how physical memory addresses convert to actual DRAM storage locations at the hardware logic layer, allowing unprivileged software to reach isolated platform memory regions without triggering security faults or exceptions. The vulnerability affects AMD Family 14h, 15h, and 16h processors and undermines foundational assumptions about how modern processors protect sensitive data.
The exploit works by changing configuration bits like BankSwizzleMode inside memory controller translation registers, which fundamentally alters how the controller calculates DRAM bank, row, and column coordinates. Because existing security boundaries—including hypervisor Extended Page Tables, System Management Mode TSEG range limits, and Platform Security Processor private carveouts—operate at the core and system fabric interconnect layer before memory traffic reaches the controller, they only validate the untranslated physical address. This means bit-flips allow standard memory accesses to land silently inside protected hardware enclaves, bypassing upstream security filters entirely. Once the address mapping is resolved through automated probing scripts using a coupon-collector heuristic and SMT solver modeling, the exploit can execute targeted read and write operations against previously impenetrable enclaves, including System Management Mode RAM, PSP firmware tables, CC6 processor sleep save areas, and microcode patch buffers.
To extract data from scrambled memory without crashing the host operating system, the exploit uses a multi-stage software pipeline that includes a custom Linux kernel module. The module takes non-boot CPU cores offline, flushes system caches, pre-warms translation lookaside buffers, and disables interrupts to maintain memory stability during rewiring. The accompanying toolchain models the physical address permutation using Galois Field arithmetic and employs an SMT solver to derive the exact bitwise mapping. The findings reveal what the report calls "a critical architectural blind spot": upstream security checks can't guarantee integrity if downstream memory controller logic permits dynamic address swizzling, posing risks to bare-metal cloud and confidential computing.
The report explains that the vulnerability highlights a vital distinction between CPU and platform privilege that modern security architectures have overlooked. While the affected AMD processors allow Ring 0 software to manipulate these memory controller configurations, this access level is fundamentally insufficient because it treats the kernel as inherently trusted. The reality of adversarial kernels—malicious or compromised operating system kernels—means that security-critical platform configuration must be managed by boundaries elevated above CPU-level privilege. Experts in hardware security and reverse-engineering communities on platforms like Reddit and podcasts such as SANS ISC Stormcast have noted the architectural implications, emphasizing that because platform security fences exist above the memory controller, they remain oblivious to the scrambling of raw physical coordinates.
To secure future systems, hardware teams must ensure memory controller translation registers are strictly locked during boot, the report concludes. The exploit requires Ring 0 privileges and primarily targets registers accessible on older AMD Family 15h and 16h processors, which limits its immediate practical threat surface. However, the discovery exposes a foundational assumption that physical addresses map deterministically to specific silicon storage locations—an assumption that upstream architectural memory fences and fault exceptions rely upon. Organizations running confidential computing workloads or bare-metal cloud infrastructure on affected AMD processor families face potential exposure until hardware-enforced register locking becomes standard. The distinction between what the CPU can control and what the platform must enforce will shape how chip manufacturers design memory security boundaries in next-generation architectures. As adversarial kernel scenarios become more common in multi-tenant and cloud environments, the industry will need to rethink where trust boundaries truly belong in the hardware stack.